Timing and Congestion Driven Algorithms for Fpga Placement
نویسندگان
چکیده
Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR. ACKNOWLEDGMENTS I have been fortunate to have my parents over the past 28 years. They always support me whenever I was ambitious or in depression. Without them, I can never be strong enough to stand success and failure. I dedicate this thesis to them. I joined the department of computer science and engineering of UNT in Fall 2005. From that moment, I received great help from a lot of professors and friends. Dr. Hao Li is my major professor who taught me a lot in the field of VLSI CAD. His encouragement and invaluable advice really motivated me to work hard on research and this thesis. Dr. Farhad Shahrokhi, who impressed me by his profound knowledge, gave me a lot of insight into graph theory. He spent much time attending the events hosted by the Chinese Student and Scholar Association. R. Mikler improved my understanding of compiler, programming languages and operating system. Dr. Saraju P. Mohanty shared tips of writing a paper with me. I am grateful to all of them. I also appreciate my friends who helped me and shared my happiness. I am thankful to friends are my great fortune. I will never forget this precious period we enjoyed together. ii CONTENTS ACKNOWLEDGMENTS ii LIST OF TABLES v LIST OF FIGURES vi
منابع مشابه
New Ant Colony Algorithm Method based on Mutation for FPGA Placement Problem
Many real world problems can be modelled as an optimization problem. Evolutionary algorithms are used to solve these problems. Ant colony algorithm is a class of evolutionary algorithms that have been inspired of some specific ants looking for food in the nature. These ants leave trail pheromone on the ground to mark good ways that can be followed by other members of the group. Ant colony optim...
متن کاملDiscrete Multi Objective Particle Swarm Optimization Algorithm for FPGA Placement (RESEARCH NOTE)
Placement process is one of the vital stages in physical design. In this stage, modules and elements of circuit are placed in distinct locations according to optimization basis. So that, each placement process tries to influence on one or more optimization factor. In the other hand, it can be told unequivocally that FPGA is one of the most important and applicable devices in our electronic worl...
متن کاملAPR: An Architecture-Driven Metric for Simultaneous Placement and Global Routing for FPGAs
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, congestion, etc) based on geometric distance and/or channel density is no longer accurate for FPGAs. Researchers have shown that the number of segments, instead of geometric (Manhattan) distance, traveled by a net is the ...
متن کاملRippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs
As a good trade-off between CPU and ASIC, FPGA is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques, such as (i) smooth stair-step flow, (ii)...
متن کاملA new less memory intensive net model for timing-driven analytical placement
We introduce a new hybrid net model for timing-driven analytical placement. This new hybrid net model decreases the average critical path delay obtained after global placement with 14% compared to wire-length-driven analytical placement. The obtained HPWL (Half Perimeter Wire-Length) remains the same. This is a very interesting feature of the hybrid net model. We also introduce a new gradual le...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2007